View SCH-V_1057931.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

lh28f008sc-v/SCH-V description the lh28f008sc-v/SCH-V flash memories with smart 5 technology are high-density, low-cost, nonvolatile, read/write storage solution for a wide range of applications. their symmetrically-blocked architecture, flexible voltage and enhanced cycling capability provide for highly flexible component suitable for resident flash arrays, simms and memory cards. their enhanced suspend capabilities provide for an ideal solution for code + data storage applications. for secure code storage applications, such as networking, where code is either directly executed out of flash or downloaded to dram, the lh28f008sc-v/SCH-V offer three levels of protection : absolute protection with v pp at gnd, selective hardware block locking, or flexible software block locking. these alternatives give designers ultimate control of their code security needs. features ? smart 5 technology C5 v v cc C 5 v or 12 v v pp ? high performance read access time lh28f008sc-v85/SCH-V85 C 85 ns (5.00.25 v)/90 ns (5.00.5 v) lh28f008sc-v12/SCH-V12 C 120 ns (5.00.5 v) ? enhanced automated suspend options C byte write suspend to read C block erase suspend to byte write C block erase suspend to read ? enhanced data protection features C absolute protection with v pp = gnd C flexible block locking C block erase/byte write lockout during power transitions ? sram-compatible write interface ? high-density symmetrically-blocked architecture C sixteen 64 k-byte erasable blocks ? enhanced cycling capability C 100 000 block erase cycles C 1.6 million block erase cycles/chip ? low power management C deep power-down mode C automatic power saving mode decreases i cc in static mode ? automated byte write and block erase C command user interface C status register ? etox tm * v nonvolatile flash technology ? packages C 40-pin tsop type i (tsop040-p-1020) normal bend/reverse bend C 44-pin sop (sop044-p-0600) C 48-ball csp (fbga048-p-0608) * etox is a trademark of intel corporation. - 1 - in the absence of confirmation by device specification sheets, sharp takes no responsibility for any defects that may occur in equipment using any sharp devices shown in catalogs, data books, etc. contact sharp in order to obtain the latest device specification sheets before using any sharp device. lh28f008sc-v/SCH-V 8 m-bit (1 mb x 8) smart 5 flash memories dc characteristics versions operating temperature v cc deep power-down current (max.) lh28f008sc-v 0 to +70 ? c 10 a lh28f008SCH-V C25 to +85 ? c 20 a comparison table
lh28f008sc-v/SCH-V - 2 - 44-pin sop (sop044-p-0600) v pp rp# a 11 a 10 a 9 a 8 a 7 a 6 a 5 a 4 nc nc a 3 a 2 a 1 a 0 dq 0 dq 1 dq 2 dq 3 gnd gnd 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 v cc ce# a 12 a 13 a 14 a 15 a 16 a 17 a 18 a 19 nc nc nc nc we# oe# ry/by# dq 7 dq 6 dq 5 dq 4 v cc 40-pin tsop (type i) (tsop040-p-1020) a 19 a 18 a 17 a 16 a 15 a 14 a 13 a 12 ce# v cc v pp rp# a 11 a 10 a 9 a 8 a 7 a 6 a 5 a 4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 nc nc we# oe# ry/by# dq 7 dq 6 dq 5 dq 4 v cc gnd gnd dq 3 dq 2 dq 1 dq 0 a 0 a 1 a 2 a 3 a 5 1 a a 6 b a 4 c a 3 d a 1 e a 2 a 8 2 a 9 a 7 a 0 dq 1 dq 0 a 11 v pp v cc 3 a 10 dq 2 gnd dq 3 4 nc nc nc gnd 5 nc nc nc nc v cc a 12 6 ce# a 13 dq 6 dq 4 dq 5 a 15 7 a 14 a 16 ry/by# dq 7 nc a 18 8 a 17 a 19 nc oe# we# f nc rp# (fbga048-p-0608) 48-ball csp note : reverse bend available on request. top view pin connections
lh28f008sc-v/SCH-V - 3 - block diagram y gating y decoder input buffer output buffer dq 0 -dq 7 v cc ce# we# oe# rp# address latch data comparator program/erase voltage switch status register command user interface write state machine data register output multiplexer identifier register address counter a 0 -a 19 x decoder 16 64 k-byte blocks ry/by# v cc gnd v pp input buffer i/o logic
lh28f008sc-v/SCH-V - 4 - symbol type name and function a 0 -a 19 input address inputs : inputs for addresses during read and write operations. addresses are internally latched during a write cycle. input/ data input/outputs : inputs data and commands during cui write cycles; outputs data during memory array, status register, and identifier code read cycles. data pins float to high-impedance when the chip is deselected or outputs are disabled. data is internally latched during a write cycle. ce# input chip enable : activates the device's control logic, input buffers, decoders, and sense amplifiers. ce#-high deselects the device and reduces power consumption to standby levels. reset/deep power-down : puts the device in deep power-down mode and resets internal automation. rp#-high enables normal operation. when driven low, rp# inhibits write operations which provide data protection during power transitions. exit from deep power-down sets the device to read array mode. rp# at v hh enables setting of the master lock-bit and enables configuration of block lock-bits when the master lock-bit is set. rp# = v hh overrides block lock-bits thereby enabling block erase and byte write operations to locked memory blocks. block erase, byte write, or lock-bit configuration with v ih rp# v hh produce spurious results and should not be attempted. oe# input output enable : gates the device's outputs during a read cycle. we# input write enable : controls writes to the cui and array blocks. addresses and data are latched on the rising edge of the we# pulse. ready/busy : indicates the status of the internal wsm. when low, the wsm is performing an internal operation (block erase, byte write, or lock-bit configuration). ry/by#-high indicates that the wsm is ready for new commands, block erase is suspended, and byte write is inactive, byte write is suspended, or the device is in deep power-down mode. ry/by# is always active and does not float when the chip is deselected or data outputs are disabled. block erase, byte write, lock-bit configuration power supply : for erasing array blocks, writing bytes, or configuring lock-bits. with v pp v pplk , memory contents cannot be altered. block erase, byte write, and lock-bit configuration with an invalid v pp (see section 6.2.3 "dc characteristics" ) produce spurious results and should not be attempted. device power supply : internal detection configures the device for 5 v operation. do not float any power pins. with v cc v lko , all write attempts to the flash memory are inhibited. device operations at invalid v cc voltage (see section 6.2.3 "dc characteristics" ) produce spurious results and should not be attempted. gnd supply ground : do not float any ground pins. nc no connect : lead is not internal connected; recommend to be floated. output dq 0 -dq 7 pin description rp# input ry/by# output v pp supply v cc supply
v cc voltage v pp voltage 5 v 5 v, 12 v lh28f008sc-v/SCH-V 1 introduction this datasheet contains lh28f008sc-v/SCH-V specifications. section 1 provides a flash memory overview. sections 2, 3, 4, and 5 describe the memory organization and functionality. section 6 covers electrical specifications. lh28f008sc-v/ SCH-V flash memories documentation also includes ordering information which is referenced in section 7. 1.1 new features lh28f008sc-v/SCH-V smart 5 flash memories maintain backwards-compatibility with the lh28f008sa. key enhancements over the lh28f008sa include : ? smart 5 technology ? enhanced suspend capabilities ? in-system block locking both devices share a compatible pinout, status register, and software command set. these similarities enable a clean upgrade from the lh28f008sa to lh28f008sc-v/SCH-V. when upgrading, it is important to note the following differences : ? because of new feature support, the two devices have different device codes. this allows for software optimization. ?v pplk has been lowered from 6.5 v to 1.5 v to support 5 v block erase, byte write, and lock-bit configuration operations. designs that switch v pp off during read operations should make sure that the v pp voltage transitions to gnd. ? to take advantage of smart 5 technology, allow v pp connection to 5 v. 1.2 product overview the lh28f008sc-v/SCH-V are high-performance 8 m-bit smart 5 flash memories organized as 1 m- byte of 8 bits. the 1 m-byte of data is arranged in sixteen 64 k-byte blocks which are individually erasable, lockable, and unlockable in-system. the memory map is shown in fig.1. smart 5 technology provides a choice of v cc and v pp combinations, as shown in table 1 , to meet system performance and power expectations. v pp at 5 v eliminates the need for a separate 12 v converter, while v pp = 12 v maximizes block erase and byte write performance. in addition to flexible erase and program voltages, the dedicated v pp pin gives complete data protection when v pp v pplk . table 1 v cc and v pp voltage combinations offered by smart 5 technology internal v cc and v pp detection circuitry auto- matically configures the device for optimized read and write operations. a command user interface (cui) serves as the interface between the system processor and internal operation of the device. a valid command sequence written to the cui initiates device automation. an internal write state machine (wsm) automatically executes the algorithms and timings necessary for block erase, byte write, and lock-bit configuration operations. a block erase operation erases one of the devices 64 k-byte blocks typically within 1 second (5 v v cc , 12 v v pp ) independent of other blocks. each block can be independently erased 100 000 times (1.6 million block erases per device). block erase suspend mode allows system software to suspend block erase to read data from, or write data to any other block. writing memory data is performed in byte increments typically within 6 s (5 v v cc , 12 v v pp ). byte write suspend mode enables the system - 5 -
lh28f008sc-v/SCH-V to read data from, or write data to any other flash memory array location. individual block locking uses a combination of bits, sixteen block lock-bits and a master lock-bit, to lock and unlock blocks. block lock-bits gate block erase and byte write operations, while the master lock-bit gates block lock-bit modification. lock-bit configuration operations (set block lock-bit, set master lock-bit, and clear block lock-bits commands) set and cleared lock-bits. the status register indicates when the wsm s block erase, byte write, or lock-bit configuration operation is finished. the ry/by# output gives an additional indicator of wsm activity by providing both a hardware signal of status (versus software polling) and status masking (interrupt masking for background block erase, for example). status polling using ry/by# minimizes both cpu overhead and system power consumption. when low, ry/by# indicates that the wsm is performing a block erase, byte write, or lock-bit configuration. ry/by#-high indicates that the wsm is ready for a new command, block erase is suspended (and byte write is inactive), byte write is suspended, or the device is in deep power-down mode. the access time is 85 ns (t avqv ) at the v cc supply voltage range of 4.75 to 5.25 v over the temperature range, 0 to +70?c (lh28f008sc-v)/ C25 to +85?c (lh28f008SCH-V). at 4.5 to 5.5 v v cc , the access time is 90 ns or 120 ns. the automatic power saving (aps) feature substantially reduces active current when the device is in static mode (addresses not switching). in aps mode, the typical i ccr current is 1 ma at 5 v v cc . when ce# and rp# pins are at v cc , the i cc cmos standby mode is enabled. when the rp# pin is at gnd, deep power-down mode is enabled which minimizes power consumption and provides write protection during reset. a reset time (t phqv ) is required from rp# switching high until outputs are valid. likewise, the device has a wake time (t phel ) from rp#-high until writes to the cui are recognized. with rp# at gnd, the wsm is reset and the status register is cleared. fig. 1 memory map 64 k-byte block 64 k-byte block 64 k-byte block 64 k-byte block 64 k-byte block 64 k-byte block 64 k-byte block 64 k-byte block 64 k-byte block 64 k-byte block 64 k-byte block 64 k-byte block 64 k-byte block 64 k-byte block 64 k-byte block 64 k-byte block fffff f0000 effff e0000 dffff cffff d0000 c0000 bffff b0000 affff a0000 9ffff 90000 8ffff 80000 7ffff 70000 6ffff 60000 5ffff 50000 4ffff 40000 3ffff 30000 2ffff 20000 1ffff 10000 0ffff 00000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - 6 -
lh28f008sc-v/SCH-V 2 principles of operation the lh28f008sc-v/SCH-V smart 5 flash memories include an on-chip wsm to manage block erase, byte write, and lock-bit configuration functions. it allows for : 100% ttl-level control inputs, fixed power supplies during block erasure, byte write, and lock-bit configuration, and minimal processor overhead with ram-like interface timings. after initial device power-up or return from deep power-down mode (see table 2 "bus operations" ), the device defaults to read array mode. manipulation of external memory control pins allow array read, standby, and output disable operations. status register and identifier codes can be accessed through the cui independent of the v pp voltage. high voltage on v pp enables successful block erasure, byte writing, and lock-bit configuration. all functions associated with altering memory contentsblock erase, byte write, lock-bit configuration, status, and identifier codesare accessed via the cui and verified through the status register. commands are written using standard micro- processor write timings. the cui contents serve as input to the wsm, which controls the block erase, byte write, and lock-bit configuration. the internal algorithms are regulated by the wsm, including pulse repetition, internal verification, and margining of data. addresses and data are internally latched during write cycles. writing the appropriate command outputs array data, accesses the identifier codes, or outputs status register data. interface software that initiates and polls progress of block erase, byte write, and lock-bit configuration can be stored in any block. this code is copied to and executed from system ram during flash memory updates. after successful completion, reads are again possible via the read array command. block erase suspend allows system software to suspend a block erase to read/write data from/to blocks other than that which is suspended. byte write suspend allows system software to suspend a byte write to read data from any other flash memory array location. 2.1 data protection depending on the application, the system designer may choose to make the v pp power supply switchable (available only when memory block erases, byte writes, or lock-bit configurations are required) or hardwired to v pph1/2 . the device accommodates either design practice and encourages optimization of the processor-memory interface. when v pp v pplk , memory contents cannot be altered. the cui, with two-step block erase, byte write, or lock-bit configuration command sequences, provides protection from unwanted operations even when high voltage is applied to v pp . all write functions are disabled when v cc is below the write lockout voltage v lko or when rp# is at v il . the device s block locking capability provides additional protection from inadvertent code or data alteration by gating erase and byte write operations. 3 bus operation the local cpu reads and writes flash memory in- system. all bus cycles to or from the flash memory conform to standard microprocessor bus cycles. 3.1 read information can be read from any block, identifier codes, or status register independent of the v pp voltage. rp# can be at either v ih or v hh . the first task is to write the appropriate read mode command (read array, read identifier codes, or read status register) to the cui. upon initial device power-up or after exit from deep power- down mode, the device automatically resets to read - 7 -
lh28f008sc-v/SCH-V array mode. four control pins dictate the data flow in and out of the component : ce#, oe#, we#, and rp#. ce# and oe# must be driven active to obtain data at the outputs. ce# is the device selection control, and when active enables the selected memory device. oe# is the data output (dq 0 -dq 7 ) control and when active drives the selected memory data onto the i/o bus. we# must be at v ih and rp# must be at v ih or v hh . fig. 12 illustrates a read cycle. 3.2 output disable with oe# at a logic-high level (v ih ), the device outputs are disabled. output pins dq 0 -dq 7 are placed in a high-impedance state. 3.3 standby ce# at a logic-high level (v ih ) places the device in standby mode which substantially reduces device power consumption. dq 0 -dq 7 outputs are placed in a high-impedance state independent of oe#. if deselected during block erase, byte write, or lock-bit configuration, the device continues functioning, and consuming active power until the operation completes. 3.4 deep power-down rp# at v il initiates the deep power-down mode. in read modes, rp#-low deselects the memory, places output drivers in a high-impedance state and turns off all internal circuits. rp# must be held low for a minimum of 100 ns. time t phqv is required after return from power-down until initial memory access outputs are valid. after this wake-up interval, normal operation is restored. the cui is reset to read array mode and status register is set to 80h. during block erase, byte write, or lock-bit configuration modes, rp#-low will abort the operation. ry/by# remains low until the reset operation is complete. memory contents being altered are no longer valid; the data may be partially erased or written. time t phwl is required after rp# goes to logic-high (v ih ) before another command can be written. as with any automated device, it is important to assert rp# during system reset. when the system comes out of reset, it expects to read from the flash memory. automated flash memories provide status information when accessed during block erase, byte write, or lock-bit configuration modes. if a cpu reset occurs with no flash memory reset, proper cpu initialization may not occur because the flash memory may be providing status information instead of array data. sharp s flash memories allow proper cpu initialization following a system reset through the use of the rp# input. in this application, rp# is controlled by the same reset# signal that resets the system cpu. - 8 -
lh28f008sc-v/SCH-V 3.5 read identifier codes operation the read identifier codes operation outputs the manufacture code, device code, block lock configuration codes for each block, and the master lock configuration code (see fig. 2 ). using the manufacture and device codes, the system cpu can automatically match the device with its proper algorithms. the block lock and master lock configuration codes identify locked and unlocked blocks and master lock-bit setting. fig. 2 device identifier code memory map 3.6 write writing commands to the cui enable reading of device data and identifier codes. they also control inspection and clearing of the status register. when v pp = v pph1/2 , the cui additionally controls block erasure, byte write, and lock-bit configuration. the block erase command requires appropriate command data and an address within the block to be erased. the byte write command requires the command and address of the location to be written. set master and block lock-bit commands require the command and address within the device (master lock) or block within the device (block lock) to be locked. the clear block lock-bits command requires the command and address within the device. the cui does not occupy an addressable memory location. it is written when we# and ce# are active. the address and data needed to execute a command are latched on the rising edge of we# or ce# (whichever goes high first). standard microprocessor write timings are used. fig. 13 and fig. 14 illustrate we# and ce#-controlled write operations. 4 command definitions when the v pp voltage v pplk , read operations from the status register, identifier codes, or blocks are enabled. placing v pph1/2 on v pp enables successful block erase, byte write and lock-bit configuration operations. device operations are selected by writing specific commands into the cui. table 3 defines these commands. fffff f0004 f0003 f0002 f0001 f0000 1ffff 10004 10003 10002 10001 10000 0ffff 00004 00003 00002 00001 00000 reserved for future implementation block 15 lock configuration code block 15 block 1 block 0 (blocks 2 through 14) reserved for future implementation reserved for future implementation block 1 lock configuration code reserved for future implementation reserved for future implementation master lock configuration code block 0 lock configuration code device code manufacture code - 9 -
lh28f008sc-v/SCH-V - 10 - mode note rp# ce# oe# we# address v pp dq 0-7 ry/by# read 1, 2, 3, 8 v ih or v hh v il v il v ih xxd out x output disable 3 v ih or v hh v il v ih v ih x x high z x standby 3 v ih or v hh v ih xxxx high z x deep power-down 4 v il xxxxx high z v oh read identifier codes 8 v ih or v hh v il v il v ih see fig. 2 x( note 5) v oh write 3, 6, 7, 8 v ih or v hh v il v ih v il xxd in x table 2 bus operations notes : 1. refer to section 6.2.3 "dc characteristics" . when v pp v pplk , memory contents can be read, but not altered. 2. x can be v il or v ih for control pins and addresses, and v pplk or v pph1/2 for v pp . see section 6.2.3 "dc characteristics" for v pplk and v pph1/2 voltages. 3. ry/by# is v ol when the wsm is executing internal block erase, byte write, or lock-bit configuration algorithms. it is v oh during when the wsm is not busy, in block erase suspend mode (with byte write inactive), byte write suspend mode, or deep power-down mode. 4. rp# at gnd0.2 v ensures the lowest deep power- down current. 5. see section 4.2 for read identifier code data. 6. command writes involving block erase, byte write, or lock-bit configuration are reliably executed when v pp = v pph1/2 and v cc = v cc1/2 . block erase, byte write, or lock-bit configuration with v ih < rp# < v hh produce spurious results and should not be attempted. 7. refer to table 3 for valid d in during a write operation. 8. don t use the timing both oe# and we# are v il .
lh28f008sc-v/SCH-V - 11 - notes : 1. bus operations are defined in table 2 . 2. x = any valid address within the device. ia = identifier code address : see fig. 2 . ba = address within the block being erased or locked. wa = address of memory location to be written. 3. srd = data read from status register. see table 6 for a description of the status register bits. wd = data to be written at location wa. data is latched on the rising edge of we# or ce# (whichever goes high first). id = data read from identifier codes. 4. following the read identifier codes command, read operations access manufacture, device, block lock, and master lock codes. see section 4.2 for read identifier code data. 5. if the block is locked, rp# must be at v hh to enable block erase or byte write operations. attempts to issue a block erase or byte write to a locked block while rp# is v ih . 6. either 40h or 10h is recognized by the wsm as the byte write setup. 7. if the master lock-bit is set, rp# must be at v hh to set a block lock-bit. rp# must be at v hh to set the master lock-bit. if the master lock-bit is not set, a block lock-bit can be set while rp# is v ih . 8. if the master lock-bit is set, rp# must be at v hh to clear block lock-bits. the clear block lock-bits operation simultaneously clears all block lock-bits. if the master lock-bit is not set, the clear block lock-bits command can be done while rp# is v ih . 9. commands other than those shown above are reserved by sharp for future device implementations and should not be used. command bus cycles note first bus cycle second bus cycle req d. oper (note 1) addr (note 2) data (note 3) oper (note 1) addr (note 2) data (note 3) read array/reset 1 write x ffh read identifier codes 3 2 4 write x 90h read ia id read status register 2 write x 70h read x srd clear status register 1 write x 50h block erase 2 5 write ba 20h write ba d0h byte write 2 5, 6 write wa 40h or 10h write wa wd block erase and 1 5 write x b0h byte write suspend block erase and 1 5 write x d0h byte write resume set block lock-bit 2 7 write ba 60h write ba 01h set master lock-bit 2 7 write x 60h write x f1h clear block lock-bits 2 8 write x 60h write x d0h table 3 command definitions (note 9)
lh28f008sc-v/SCH-V - 12 - 4.1 read array command upon initial device power-up and after exit from deep power-down mode, the device defaults to read array mode. this operation is also initiated by writing the read array command. the device remains enabled for reads until another command is written. once the internal wsm has started a block erase, byte write or lock-bit configuration, the device will not recognize the read array command until the wsm completes its operation unless the wsm is suspended via an erase suspend or byte write suspend command. the read array command functions independently of the v pp voltage and rp# can be v ih or v hh . 4.2 read identifier codes command the identifier code operation is initiated by writing the read identifier codes command. following the command write, read cycles from addresses shown in fig. 2 retrieve the manufacture, device, block lock configuration and master lock configuration codes (see table 4 for identifier code values). to terminate the operation, write another valid command. like the read array command, the read identifier codes command functions independently of the v pp voltage and rp# can be v ih or v hh . following the read identifier codes command, the following information can be read : table 4 identifier codes note : 1. x selects the specific block lock configuration code to be read. see fig. 2 for the device identifier code memory map. 4.3 read status register command the status register may be read to determine when a block erase, byte write, or lock-bit configuration is complete and whether the operation completed successfully. it may be read at any time by writing the read status register command. after writing this command, all subsequent read operations output data from the status register until another valid command is written. the status register contents are latched on the falling edge of oe# or ce#, whichever occurs. oe# or ce# must toggle to v ih before further reads to update the status register latch. the read status register command functions independently of the v pp voltage. rp# can be v ih or v hh . 4.4 clear status register command status register bits sr.5, sr.4, sr.3, and sr.1 are set to "1"s by the wsm and can only be reset by the clear status register command. these bits indicate various failure conditions (see table 6 ). by allowing system software to reset these bits, several operations (such as cumulatively erasing or locking multiple blocks or writing several bytes in sequence) may be performed. the status register may be polled to determine if an error occurred during the sequence. to clear the status register, the clear status register command (50h) is written. it functions independently of the applied v pp voltage. rp# can be v ih or v hh . this command is not functional during block erase or byte write suspend modes. 4.5 block erase command erase is executed one block at a time and initiated by a two-cycle command. a block erase setup is first written, followed by a block erase confirm. this command sequence requires appropriate sequencing and an address within the block to be erased (erase changes all block data to ffh). block preconditioning, erase, and verify are handled internally by the wsm (invisible to the system). after the two-cycle block erase sequence is written, code address data manufacture code 00000h 89 device code 00001h a6 block lock configuration x0002h (note 1) ? block is unlocked dq 0 = 0 ? block is locked dq 0 = 1 ? reserved for future use dq 1-7 master lock configuration 00003h ? device is unlocked dq 0 = 0 ? device is locked dq 0 = 1 ? reserved for future use dq 1-7
lh28f008sc-v/SCH-V the device automatically outputs status register data when read (see fig. 3 ). the cpu can detect block erase completion by analyzing the output data of the ry/by# pin or status register bit sr.7. when the block erase is complete, status register bit sr.5 should be checked. if a block erase error is detected, the status register should be cleared before system software attempts corrective actions. the cui remains in read status register mode until a new command is issued. this two-step command sequence of set-up followed by execution ensures that block contents are not accidentally erased. an invalid block erase command sequence will result in both status register bits sr.4 and sr.5 being set to "1". also, reliable block erasure can only occur when v cc = v cc1/2 and v pp = v pph1/2 . in the absence of this high voltage, block contents are protected against erasure. if block erase is attempted while v pp v pplk , sr.3 and sr.5 will be set to "1". successful block erase requires that the corresponding block lock-bit be cleared or, if set, that rp# = v hh . if block erase is attempted when the corresponding block lock-bit is set and rp# = v ih , sr.1 and sr.5 will be set to "1". block erase operations with v ih < rp# < v hh produce spurious results and should not be attempted. 4.6 byte write command byte write is executed by a two-cycle command sequence. byte write setup (standard 40h or alternate 10h) is written, followed by a second write that specifies the address and data (latched on the rising edge of we#). the wsm then takes over, controlling the byte write and write verify algorithms internally. after the byte write sequence is written, the device automatically outputs status register data when read (see fig. 4 ). the cpu can detect the completion of the byte write event by analyzing the ry/by# pin or status register bit sr.7. when byte write is complete, status register bit sr.4 should be checked. if byte write error is detected, the status register should be cleared. the internal wsm verify only detects errors for "1"s that do not successfully write to "0"s. the cui remains in read status register mode until it receives another command. reliable byte writes can only occur when v cc = v cc1/2 and v pp = v pph1/2 . in the absence of this high voltage, memory contents are protected against byte writes. if byte write is attempted while v pp v pplk , status register bits sr.3 and sr.4 will be set to "1". successful byte write requires that the corresponding block lock-bit be cleared or, if set, that rp# = v hh . if byte write is attempted when the corresponding block lock-bit is set and rp# = v ih , sr.1 and sr.4 will be set to "1". byte write operations with v ih < rp# < v hh produce spurious results and should not be attempted. 4.7 block erase suspend command the block erase suspend command allows block erase interruption to read or byte write data in another block of memory. once the block erase process starts, writing the block erase suspend command requests that the wsm suspend the block erase sequence at a predetermined point in the algorithm. the device outputs status register data when read after the block erase suspend command is written. polling status register bits sr.7 and sr.6 can determine when the block erase operation has been suspended (both will be set to "1"). ry/by# will also transition to v oh . specification t whrh2 defines the block erase suspend latency. at this point, a read array command can be written to read data from blocks other than that which is suspended. a byte write command sequence can also be issued during erase suspend to program data in other blocks. using the byte - 13 -
lh28f008sc-v/SCH-V write suspend command (see section 4.8 ), a byte write operation can also be suspended. during a byte write operation with block erase suspended, status register bit sr.7 will return to "0" and the ry/by# output will transition to v ol . however, sr.6 will remain "1" to indicate block erase suspend status. the only other valid commands while block erase is suspended are read status register and block erase resume. after a block erase resume command is written to the flash memory, the wsm will continue the block erase process. status register bits sr.6 and sr.7 will automatically clear and ry/by# will return to v ol . after the erase resume command is written, the device automatically outputs status register data when read (see fig. 5 ). v pp must remain at v pph1/2 (the same v pp level used for block erase) while block erase is suspended. rp# must also remain at v ih or v hh (the same rp# level used for block erase). block erase cannot resume until byte write operations initiated during block erase suspend have completed. 4.8 byte write suspend command the byte write suspend command allows byte write interruption to read data in other flash memory locations. once the byte write process starts, writing the byte write suspend command requests that the wsm suspend the byte write sequence at a predetermined point in the algorithm. the device continues to output status register data when read after the byte write suspend command is written. polling status register bits sr.7 and sr.2 can determine when the byte write operation has been suspended (both will be set to "1"). ry/by# will also transition to v oh . specification t whrh1 defines the byte write suspend latency. at this point, a read array command can be written to read data from locations other than that which is suspended. the only other valid commands while byte write is suspended are read status register and byte write resume. after byte write resume command is written to the flash memory, the wsm will continue the byte write process. status register bits sr.2 and sr.7 will automatically clear and ry/by# will return to v ol . after the byte write resume command is written, the device automatically outputs status register data when read (see fig. 6 ). v pp must remain at v pph1/2 (the same v pp level used for byte write) while in byte write suspend mode. rp# must also remain at v ih or v hh (the same rp# level used for byte write). 4.9 set block and master lock-bit commands a flexible block locking and unlocking scheme is enabled via a combination of block lock-bits and a master lock-bit. the block lock-bits gate program and erase operations while the master lock-bit gates block-lock bit modification. with the master lock-bit not set, individual block lock-bits can be set using the set block lock-bit command. the set master lock-bit command, in conjunction with rp# = v hh , sets the master lock-bit. after the master lock-bit is set, subsequent setting of block lock-bits requires both the set block lock-bit command and v hh on the rp# pin. see table 5 for a summary of hardware and software write protection options. set block lock-bit and master lock-bit are executed by a two-cycle command sequence. the set block or master lock-bit setup along with appropriate block or device address is written followed by either the set block lock-bit confirm (and an address within the block to be locked) or the set master lock-bit confirm (and any device address). the wsm then controls the set lock-bit algorithm. after the sequence is written, the device automatically outputs status register data when read (see fig. 7 ). the cpu can detect the completion of the set lock- bit event by analyzing the ry/by# pin output or status register bit sr.7. - 14 -
lh28f008sc-v/SCH-V when the set lock-bit operation is complete, status register bit sr.4 should be checked. if an error is detected, the status register should be cleared. the cui will remain in read status register mode until a new command is issued. this two-step sequence of set-up followed by execution ensures that lock-bits are not accidentally set. an invalid set block or master lock-bit command will result in status register bits sr.4 and sr.5 being set to "1". also, reliable operations occur only when v cc = v cc1/2 and v pp = v pph1/2 . in the absence of this high voltage, lock-bit contents are protected against alteration. a successful set block lock-bit operation requires that the master lock-bit be cleared or, if the master lock-bit is set, that rp# = v hh . if it is attempted with the master lock-bit set and rp# = v ih , sr.1 and sr.4 will be set to "1" and the operation will fail. set block lock-bit operations while v ih < rp# < v hh produce spurious results and should not be attempted. a successful set master lock-bit operation requires that rp# = v hh . if it is attempted with rp# = v ih , sr.1 and sr.4 will be set to "1" and the operation will fail. set master lock-bit operations with v ih < rp# < v hh produce spurious results and should not be attempted. 4.10 clear block lock-bits command all set block lock-bits are cleared in parallel via the clear block lock-bits command. with the master lock-bit not set, block lock-bits can be cleared using only the clear block lock-bits command. if the master lock-bit is set, clearing block lock-bits requires both the clear block lock-bits command and v hh on the rp# pin. see table 5 for a summary of hardware and software write protection options. clear block lock-bits operation is executed by a two-cycle command sequence. a clear block lock- bits setup is first written. after the command is written, the device automatically outputs status register data when read (see fig. 8 ). the cpu can detect completion of the clear block lock-bits event by analyzing the ry/by# pin output or status register bit sr.7. when the operation is complete, status register bit sr.5 should be checked. if a clear block lock-bits error is detected, the status register should be cleared. the cui will remain in read status register mode until another command is issued. this two-step sequence of set-up followed by execution ensures that block lock-bits are not accidentally cleared. an invalid clear block lock- bits command sequence will result in status register bits sr.4 and sr.5 being set to "1". also, a reliable clear block lock-bits operation can only occur when v cc = v cc1/2 and v pp = v pph1/2 . if a clear block lock-bits operation is attempted while v pp v pplk , sr.3 and sr.5 will be set to "1". in the absence of this high voltage, the block lock-bit contents are protected against alteration. a successful clear block lock-bits operation requires that the master lock-bit is not set or, if the master lock-bit is set, that rp# = v hh . if it is attempted with the master lock-bit set and rp# = v ih , sr.1 and sr.5 will be set to "1" and the operation will fail. a clear block lock-bits operation with v ih < rp# < v hh produce spurious results and should not be attempted. if a clear block lock-bits operation is aborted due to v pp or v cc transition out of valid range or rp# active transition, block lock-bit values are left in an undetermined state. a repeat of clear block lock-bits is required to initialize block lock-bit contents to known values. once the master lock-bit is set, it cannot be cleared. - 15 -
lh28f008sc-v/SCH-V - 16 - master block operation rp# effect lock-bit lock-bit block erase 0v ih or v hh block erase and byte write enabled or byte write x 1 v ih block is locked. block erase and byte write disabled v hh block lock-bit override. block erase and byte write enabled set block 0xv ih or v hh set block lock-bit enabled lock-bit 1 x v ih master lock-bit is set. set block lock-bit disabled v hh master lock-bit override. set block lock-bit enabled set master xx v ih set master lock-bit disabled lock-bit v hh set master lock-bit enabled clear block 0xv ih or v hh clear block lock-bits enabled lock-bits 1 x v ih master lock-bit is set. clear block lock-bits disabled v hh master lock-bit override. clear block lock-bits enabled table 5 write protection alternatives table 6 status register definition wsms ess eclbs bwslbs vpps bwss dps r 76543210 sr.7 = write state machine status (wsms) 1 = ready 0 = busy sr.6 = erase suspend status (ess) 1 = block erase suspended 0 = block erase in progress/completed sr.5 = erase and clear lock-bits status (eclbs) 1 = error in block erase or clear lock-bits 0 = successful block erase or clear lock-bits sr.4 = byte write and set lock-bit status (bwslbs) 1 = error in byte write or set master/block lock-bit 0= successful byte write or set master/block lock-bit sr.3 = v pp status (vpps) 1=v pp low detect, operation abort 0=v pp ok sr.2 = byte write suspend status (bwss) 1 = byte write suspended 0 = byte write in progress/completed sr.1 = device protect status (dps) 1 = master lock-bit, block lock-bit and/or rp# lock detected, operation abort 0 = unlock sr.0 = reserved for future enhancements (r) notes : check ry/by# or sr.7 to determine block erase, byte write, or lock-bit configuration completion. sr.6-0 are invalid while sr.7 = "0". if both sr.5 and sr.4 are "1"s after a block erase or lock-bit configuration attempt, an improper command sequence was entered. sr.3 does not provide a continuous indication of v pp level. the wsm interrogates and indicates the v pp level only after block erase, byte write, set block/master lock-bit, or clear block lock-bits command sequences. sr.3 is not guaranteed to reports accurate feedback only when v pp 1 v pph1/2 . sr.1 does not provide a continuous indication of master and block lock-bit values. the wsm interrogates the master lock- bit, block lock-bit, and rp# only after block erase, byte write, or lock-bit configuration command sequences. it informs the system, depending on the attempted operation, if the block lock-bit is set, master lock-bit is set, and/or rp# is not v hh . reading the block lock and master lock configuration codes after writing the read identifier codes command indicates master and block lock-bit status. sr.0 is reserved for future use and should be masked out when polling the status register.
lh28f008sc-v/SCH-V - 17 - block erase complete start write 20h, block address write d0h, block address read status register 0 sr.7 = 1 full status check if desired repeat for subsequent block erasures. full status check can be done after each block erase or after a sequence of block erasures. write ffh after the last block erase operation to place device in read array mode. bus operation write write read standby command erase setup comments data = 20h addr = within block to be erased data = d0h addr = within block to be erased status register data check sr.7 1 = wsm ready 0 = wsm busy sr.3 = full status check procedure read status register data (see above) v pp range error 1 0 sr.1 = device protect error 1 0 bus operation command comments standby standby check sr.1 1 = device protect detect rp# = v ih , block lock-bit is set only required for systems implementing lock-bit configuration check sr.5 1 = block erase error sr.5, sr.4, sr.3 and sr.1 are only cleared by the clear status register command in cases where multiple blocks are erased before full status is checked. if error is detected, clear the status register before attempting retry or other error recovery. no suspend block erase yes suspend block erase loop erase confirm block erase successful sr.4, 5 = command sequence error 1 0 sr.5 = block erase error 1 0 standby check sr.3 1 = v pp error detect standby check sr.4, 5 both 1 = command sequence error fig. 3 automated block erase flowchart
lh28f008sc-v/SCH-V - 18 - byte write complete start write 40h, address write byte data and address read status register 0 sr.7 = 1 full status check if desired repeat for subsequent byte writes. sr full status check can be done after each byte write or after a sequence of byte writes. write ffh after the last byte write operation to place device in read array mode. bus operation write write read standby command setup byte write comments data = 40h addr = location to be written data = data to be written addr = location to be written status register data check sr.7 1 = wsm ready 0 = wsm busy sr.3 = full status check procedure read status register data (see above) v pp range error 1 0 sr.1 = device protect error 1 0 bus operation command comments standby check sr.1 1 = device protect detect rp# = v ih , block lock-bit is set only required for systems implementing lock-bit configuration sr.4, sr.3 and sr.1 are only cleared by the clear status register command in cases where multiple locations are written before full status is checked. if error is detected, clear the status register before attempting retry or other error recovery. no suspend byte write yes suspend byte write loop byte write byte write successful sr.4 = byte write error 1 0 standby check sr.3 1 = v pp error detect standby check sr.4 1 = data write error fig. 4 automated byte write flowchart
lh28f008sc-v/SCH-V - 19 - block erase resumed start write b0h read status register 0 sr.7 = 1 byte write bus operation write read standby standby command erase suspend comments data = b0h addr = x status register data addr = x check sr.7 1 = wsm ready 0 = wsm busy check sr.6 1 = block erase suspended 0 = block erase completed erase resume sr.6 = done? write d0h block erase completed write ffh read array data 1 0 no yes write data = d0h addr = x read or byte write? read read array data byte write loop fig. 5 block erase suspend/resume flowchart
lh28f008sc-v/SCH-V - 20 - byte write resumed start write b0h read status register 0 sr.7 = 1 write ffh bus operation write read standby standby command byte write suspend comments data = b0h addr = x status register data addr = x check sr.7 1 = wsm ready 0 = wsm busy check sr.2 1 = byte write suspended 0 = byte write completed read array sr.2 = read array data done reading write d0h byte write completed write ffh read array data 1 0 no yes write read write byte write resume data = ffh addr = x read array locations other than that being written. data = d0h addr = x fig. 6 byte write suspend/resume flowchart
lh28f008sc-v/SCH-V - 21 - set lock-bit complete start write 60h, block/device address write 01h/f1h, block/device address read status register 0 sr.7 = 1 full status check if desired repeat for subsequent lock-bit set operations. full status check can be done after each lock-bit set operation or after a sequence of lock-bit set operations. write ffh after the last lock-bit set operation to place device in read array mode. bus operation write write read standby command set block/master lock-bit setup comments data = 60h addr = block address (block), device address (master) data = 01h (block), f1h (master) addr = block address (block), device address (master) status register data check sr.7 1 = wsm ready 0 = wsm busy sr.3 = full status check procedure read status register data (see above) v pp range error 1 0 sr.1 = device protect error 1 0 bus operation command comments standby standby check sr.1 1 = device protect detect rp# = v ih (set master lock-bit operation) rp# = v ih , master lock-bit is set (set block lock-bit operation) check sr.4 1 = set lock-bit error sr.5, sr.4, sr.3 and sr.1 are only cleared by the clear status register command in cases where multiple lock-bits are set before full status is checked. if error is detected, clear the status register before attempting retry or other error recovery. set block or master lock-bit confirm set lock-bit successful sr.4, 5 = command sequence error 1 0 sr.4 = set lock-bit error 1 0 standby check sr.3 1 = v pp error detect standby check sr.4, 5 both 1 = command sequence error fig. 7 set block and master lock-bit flowchart
lh28f008sc-v/SCH-V - 22 - clear block lock-bits complete start write 60h write d0h read status register 0 sr.7 = 1 full status check if desired write ffh after the last clear block lock-bits operation to place device in read array mode. bus operation write write read standby command clear block lock-bits setup comments data = 60h addr = x data = d0h addr = x status register data check sr.7 1 = wsm ready 0 = wsm busy sr.3 = full status check procedure read status register data (see above) v pp range error 1 0 sr.1 = device protect error 1 0 bus operation command comments standby standby check sr.1 1 = device protect detect rp# = v ih , master lock-bit is set check sr.5 1 = clear block lock-bits error sr.5, sr.4, sr.3 and sr.1 are only cleared by the clear status register command. if error is detected, clear the status register before attempting retry or other error recovery. clear block lock-bits confirm clear block lock-bits successful sr.4, 5 = command sequence error 1 0 sr.5 = clear block lock-bits error 1 0 standby check sr.3 1 = v pp error detect standby check sr.4, 5 both 1 = command sequence error fig. 8 clear block lock-bits flowchart
lh28f008sc-v/SCH-V 5 design considerations 5.1 three-line output control the device will often be used in large memory arrays. sharp provides three control inputs to accommodate multiple memory connections. three- line control provides for : a. lowest possible memory power consumption. b. complete assurance that data bus contention will not occur. to use these control inputs efficiently, an address decoder should enable ce# while oe# should be connected to all memory devices and the systems read# control line. this assures that only selected memory devices have active outputs while deselected memory devices are in standby mode. rp# should be connected to the system powergood signal to prevent unintended writes during system power transitions. powergood should also toggle during system reset. 5.2 ry/by# and block erase, byte write, and lock-bit configuration polling ry/by# is a full cmos output that provides a hardware method of detecting block erase, byte write and lock-bit configuration completion. it transitions low after block erase, byte write, or lock- bit configuration commands and returns to v oh when the wsm has finished executing the internal algorithm. ry/by# can be connected to an interrupt input of the system cpu or controller. it is active at all times. ry/by# is also v oh when the device is in block erase suspend (with byte write inactive), byte write suspend or deep power-down modes. 5.3 power supply decoupling flash memory power switching characteristics require careful device decoupling. system designers are interested in three supply current issues; standby current levels, active current levels and transient peaks produced by falling and rising edges of ce# and oe#. transient current magnitudes depend on the device outputs capacitive and inductive loading. two-line control and proper decoupling capacitor selection will suppress transient voltage peaks. each device should have a 0.1 f ceramic capacitor connected between its v cc and gnd and between its v pp and gnd. these high-frequency, low inductance capacitors should be placed as close as possible to package leads. additionally, for every eight devices, a 4.7 f electrolytic capacitor should be placed at the arrays power supply connection between v cc and gnd. the bulk capacitor will overcome voltage slumps caused by pc board trace inductance. 5.4 v pp trace on printed circuit boards updating flash memories that reside in the target system requires that the printed circuit board designers pay attention to the v pp power supply trace. the v pp pin supplies the memory cell current for byte writing and block erasing. use similar trace widths and layout considerations given to the v cc power bus. adequate v pp supply traces and decoupling will decrease v pp voltage spikes and overshoots. 5.5 v cc , v pp , rp# transitions block erase, byte write and lock-bit configuration are not guaranteed if v pp falls outside of a valid v pph1/2 range, v cc falls outside of a valid v cc1/2 range, or rp# v ih or v hh . if v pp error is detected, status register bit sr.3 is set to "1" along with sr.4 or sr.5, depending on the attempted operation. if rp# transitions to v il during block erase, byte write, or lock-bit configuration, ry/by# will remain low until the reset operation is complete. then, the operation will abort and the device will enter deep power-down. the aborted operation may leave data partially altered. therefore, the command sequence must be repeated after normal - 23 -
lh28f008sc-v/SCH-V operation is restored. device power-off or rp# transitions to v il clear the status register. the cui latches commands issued by system software and is not altered by v pp or ce# transitions or wsm actions. its state is read array mode upon power-up, after exit from deep power- down or after v cc transitions below v lko . after block erase, byte write, or lock-bit configuration, even after v pp transitions down to v pplk , the cui must be placed in read array mode via the read array command if subsequent access to the memory array is desired. 5.6 power-up/down protection the device is designed to offer protection against accidental block erasure, byte writing, or lock-bit configuration during power transitions. upon power- up, the device is indifferent as to which power supply (v pp or v cc ) powers-up first. internal circuitry resets the cui to read array mode at power-up. a system designer must guard against spurious writes for v cc voltages above v lko when v pp is active. since both we# and ce# must be low for a command write, driving either to v ih will inhibit writes. the cuis two-step command sequence architecture provides added level of protection against data alteration. in-system block lock and unlock capability prevents inadvertent data alteration. the device is disabled while rp# = v il regardless of its control inputs state. 5.7 power consumption when designing portable systems, designers must consider battery power consumption not only during device operation, but also for data retention during system idle time. flash memorys nonvolatility increases usable battery life because data is retained when system power is removed. in addition, deep power-down mode ensures extremely low power consumption even when system power is applied. for example, portable computing products and other power sensitive applications that use an array of devices for solid- state storage can consume negligible power by lowering rp# to v il standby or sleep modes. if access is again needed, the devices can be read following the t phqv and t phwl wake-up cycles required after rp# is first raised to v ih . see section 6.2.4 through 6.2.6 "ac characteristics - read-only and write operations" and fig. 12, fig. 13 and fig. 14 for more information. - 24 -
lh28f008sc-v/SCH-V 6 electrical specifications 6.1 absolute maximum ratings * operating temperature ? lh28f008sc-v during read, block erase, byte write and lock-bit configuration ........ 0 to +70c (note 1) temperature under bias ............. C10 to +80c ? lh28f008SCH-V during read, block erase, byte write and lock-bit configuration ... C 25 to +85c (note 2) temperature under bias ............. C 25 to +85c storage temperature ........................ C 65 to +125c voltage on any pin (except v cc , v pp , and rp#) .... C 2.0 to +7.0 v (note 3) v cc supply voltage ................. C 2.0 to +7.0 v (note 3) v pp update voltage during block erase, byte write and lock-bit configuration .. C 2.0 to +14.0 v (note 3, 4) rp# voltage with respect to gnd during lock-bit configuration operations .. C 2.0 to +14.0 v (note 3, 4) output short circuit current .............. 100 ma (note 5) * warning : stressing the device beyond the " absolute maximum ratings" may cause permanent damage. these are stress ratings only. operation beyond the "operating conditions" is not recommended and extended exposure beyond the "operating conditions" may affect device reliability. notes : 1. operating temperature is for commercial product defined by this specification. 2. operating temperature is for extended temperature product defined by this specification. 3. all specified voltages are with respect to gnd. minimum dc voltage is C 0.5 v on input/output pins and C 0.2 v on v cc and v pp pins. during transitions, this level may undershoot to C 2.0 v for periods < 20 ns. maximum dc voltage on input/output pins and v cc is v cc +0.5 v which, during transitions, may overshoot to v cc +2.0 v for periods < 20 ns. 4. maximum dc voltage on v pp and rp# may overshoot to +14.0 v for periods < 20 ns. 5. output shorted for no more than one second. no more than one output shorted at a time. notice : the specifications are subject to change without notice. verify with your local sharp sales office that you have the latest datasheet before finalizing a design. - 25 - symbol parameter note min. max. unit versions t a operating temperature 1 0 +70 ? c lh28f008sc-v C25 +85 ?c lh28f008SCH-V v cc1 v cc supply voltage (5.00.25 v) 4.75 5.25 v lh28f008sc-v85/SCH-V85 v cc2 v cc supply voltage (5.00.5 v) 4.50 5.50 v 6.2 operating conditions note : 1. test condition : ambient temperature
lh28f008sc-v/SCH-V - 26 - note : 1. sampled, not 100% tested. 6.2.2 ac input/output test conditions fig. 9 transient input/output reference waveform for v cc = 5.0 0.25 v (high speed testing configuration) fig. 10 transient input/output reference waveform for v cc = 5.0 0.5 v (standard testing configuration) ac test inputs are driven at 3.0 v for a logic "1" and 0.0 v for a logic "0". input timing begins, and output timing ends, at 1.5 v. input rise and fall times (10% to 90%) < 10 ns. ac test inputs are driven at v oh (2.4 v ttl ) for a logic "1" and v ol (0.45 v ttl ) for a logic "0". input timing begins at v ih (2.0 v ttl ) and v il (0.8 v ttl ). output timing ends at v ih and v il . input rise and fall times (10% to 90%) < 10 ns. symbol parameter typ. max. unit condition c in input capacitance 6 8 pf v in = 0.0 v c out output capacitance 8 12 pf v out = 0.0 v 6.2.1 capacitance (note 1) t a = +25 ? c, f = 1 mhz 1.5 1.5 3.0 0.0 test points input output 2.0 0.8 2.0 0.8 2.4 0.45 test points input output device under test c l includes jig capacitance r l = 3.3 k w c l out 1.3 v 1n914 fig. 11 transient equivalent testing load circuit note : 1. applied to high-speed products, lh28f008sc-v85 and lh28f008SCH-V85. test configuration c l (pf) v cc = 5.00.25 v (note 1) 30 v cc = 5.00.5 v 100 test configuration capacitance loading value
- 27 - lh28f008sc-v/SCH-V symbol parameter note v cc = 5.00.5 v unit test typ. max. conditions i li input load current 1 1 a v cc = v cc max. v in = v cc or gnd i lo output leakage current 1 10 a v cc = v cc max. v out = v cc or gnd cmos inputs 25 100 a v cc = v cc max. i ccs v cc standby current 1, 3, 6 ce# = rp# = v cc 0.2 v ttl inputs 0.4 2 ma v cc = v cc max. ce# = rp# = v ih i ccd v cc deep power- lh28f008sc-v 1 10 a rp# = gnd0.2 v down current lh28f008SCH-V 20 i out (ry/by#) = 0 ma cmos inputs v cc = v cc max. 17 35 ma ce# = gnd f = 8 mhz i ccr v cc read current 1, 5, 6 i out = 0 ma ttl inputs v cc = v cc max. 20 50 ma ce# = gnd f = 8 mhz i out = 0 ma i ccw v cc byte write or set lock-bit current 1, 7 35 ma v pp = 5.00.5 v 30 ma v pp = 12.00.6 v i cce v cc block erase or 1, 7 30 ma v pp = 5.00.5 v clear block lock-bits current 25 ma v pp = 12.00.6 v i ccws v cc byte write or 1, 2 1 10 ma ce# = v ih i cces block erase suspend current i pps v pp standby or read current 1 2 15 a v pp v cc i ppr 10 200 a v pp > v cc i ppd v pp deep power-down current 1 0.1 5 a rp# = gnd0.2 v i ppw v pp byte write or set lock-bit current 1, 7 40 ma v pp = 5.00.5 v 15 ma v pp = 12.00.6 v i ppe v pp block erase or 1, 7 20 ma v pp = 5.00.5 v clear block lock-bits current 15 ma v pp = 12.00.6 v i ppws v pp byte write or 1 10 200 a v pp = v pph1/2 i ppes block erase suspend current 6.2.3 dc characteristics
- 28 - lh28f008sc-v/SCH-V 6.2.3 dc characteristics (contd.) notes : 1. all currents are in rms unless otherwise noted. typical values at nominal v cc voltage and t a = +25?c. these currents are valid for all product versions (packages and speeds). 2. i ccws and i cces are specified with the device de- selected. if reading or byte writing in erase suspend mode, the devices current draw is the sum of i ccws or i cces and i ccr or i ccw , respectively. 3. includes ry/by#. 4. block erases, byte writes, and lock-bit configurations are inhibited when v pp v pplk , and not guaranteed in the range between v pplk (max.) and v pph1 (min.), between v pph1 (max.) and v pph2 (min.), and above v pph2 (max.). 5. automatic power saving (aps) reduces typical i ccr to 1 ma at 5 v v cc in static operation. 6. cmos inputs are either v cc 0.2 v or gnd0.2 v. ttl inputs are either v il or v ih . 7. sampled, not 100% tested. 8. master lock-bit set operations are inhibited when rp# = v ih . block lock-bit configuration operations are inhibited when the master lock-bit is set and rp# = v ih . block erases and byte writes are inhibited when the corresponding block lock-bit is set and rp# = v ih . block erase, byte write, and lock-bit configuration operations are not guaranteed with v ih < rp# < v hh and should not be attempted. 9. rp# connection to a v hh supply is allowed for a maximum cumulative period of 80 hours. symbol parameter note v cc = 5.00.5 v unit test min. max. conditions v il input low voltage 7 C 0.5 0.8 v v ih input high voltage 7 2.0 v cc v +0.5 v ol output low voltage 3, 7 0.45 v v cc = v cc min. i ol = 5.8 ma v oh1 output high voltage 3, 7 2.4 v v cc = v cc min. (ttl) i oh = C2.5 ma 0.85 v v cc = v cc min. v oh2 output high voltage 3, 7 v cc i oh = C2.5 ma (cmos) v cc v v cc = v cc min. C 0.4 i oh = C100 a v pplk v pp lockout voltage during 4, 7 1.5 v normal operations v pph1 v pp voltage during byte write, 4.5 5.5 v block erase or lock-bit operations v pph2 v pp voltage during byte write, 11.4 12.6 v block erase or lock-bit operations v lko v cc lockout voltage 2.0 v set master lock-bit v hh rp# unlock voltage 8, 9 11.4 12.6 v override master and block lock-bit
- 29 - symbol parameter note min. max. min. max. min. max. t avav read cycle time 85 90 120 ns t avqv address to output delay 85 90 120 ns t elqv ce# to output delay 2 85 90 120 ns t phqv rp# high to output delay 400 400 400 ns t glqv oe# to output delay 2 40 45 50 ns t elqx ce# to output in low z 3 0 0 0 ns t ehqz ce# high to output in high z 3 55 55 55 ns t glqx oe# to output in low z 3 0 0 0 ns t ghqz oe# high to output in high z 3 10 10 15 ns output hold from address, t oh ce# or oe# change, 3 0 0 0 ns whichever occurs first lh28f008sc-v/SCH-V versions notes : 1. see ac input/output reference waveform ( fig. 9 and fig. 10 ) for maximum allowable input slew rate. 2. oe# may be delayed up to t elqv -t glqv after the falling edge of ce# without impact on t elqv . 3. sampled, not 100% tested. 4. see fig. 9 "transient input/output reference waveform" and fig. 11 "transient equivalent testing load circuit" (high speed configuration) for testing characteristics. 5. see fig. 10 "transient input/output reference waveform" and fig. 11 "transient equivalent testing load circuit" (standard configuration) for testing characteristics. 6.2.4 ac characteristics - read-only operations (note 1) ? v cc = 5.00.25 v, 5.00.5 v, t a = 0 to +70?c or C 25 to +85 ? c v cc 0.25 v v cc 0.5 v (note 4) lh28f008sc-v85/ lh28f008SCH-V85 (note 5) lh28f008sc-v12/ lh28f008SCH-V12 (note 5) lh28f008sc-v85/ lh28f008SCH-V85 unit
lh28f008sc-v/SCH-V - 30 - v ol v oh standby device address selection data valid addresses (a) v il v il v il v ih v ih v ih v ih v il v il ce# (e) oe# (g) we# (w) data (d/q) (dq 0 - dq 7 ) rp# (p) v cc high z high z t avav t ehqz t ghqz t oh t glqv t elqv t glqx t elqx t avqv t phqv valid output v ih address stable fig. 12 ac waveform for read operations
lh28f008sc-v/SCH-V - 31 - 6.2.5 ac characteristics - write operation (note 1) ? v cc = 5.00.25 v, 5.00.5 v, t a = 0 to +70?c or C 25 to +85 ? c notes : 1. read timing characteristics during block erase, byte write and lock-bit configuration operations are the same as during read-only operations. refer to section 6.2.4 "ac characteristics" for read-only operations. 2. sampled, not 100% tested. 3. refer to table 3 for valid a in and d in for block erase, byte write, or lock-bit configuration. 4. v pp should be held at v pph1/2 (and if necessary rp# should be held at v hh ) until determination of block erase, byte write, or lock-bit configuration success (sr.1/3/4/5 = 0). 5. see fig. 9 "transient input/output reference waveform" and fig. 11 "transient equivalent testing load circuit" (high seed configuration) for testing characteristics. 6. see fig. 10 "transient input/output reference waveform" and fig. 11 "transient equivalent testing load circuit" (standard configuration) for testing characteristics. symbol parameter note min. max. min. max. min. max. t avav write cycle time 85 90 120 ns t phwl rp# high recovery to we# 2111s going low t elwl ce# setup to we# going low 10 10 10 ns t wlwh we# pulse width 40 40 40 ns t phhwh rp# v hh setup to we# going high 2 100 100 100 ns t vpwh v pp setup to we# going high 2 100 100 100 ns t avwh address setup to we# going high 3404040ns t dvwh data setup to we# going high 3 40 40 40 ns t whdx data hold from we# high 5 5 5 ns t whax address hold from we# high 5 5 5 ns t wheh ce# hold from we# high 10 10 10 ns t whwl we# pulse width high 30 30 30 ns t whrl we# high to ry/by# going low 90 90 90 ns t whgl write recovery before read 0 0 0 ns t qvvl v pp hold from valid srd, 2, 4 0 0 0 ns ry/by# high t qvph rp# v hh hold from valid srd, 2, 4 0 0 0 ns ry/by# high versions v cc 0.25 v v cc 0.5 v (note 5) lh28f008sc-v85/ lh28f008SCH-V85 (note 6) lh28f008sc-v12/ lh28f008SCH-V12 (note 6) lh28f008sc-v85/ lh28f008SCH-V85 unit
lh28f008sc-v/SCH-V - 32 - v pp (v) v ih v ih v ih v ih v ih v oh v ol v ih v il v il v il v il v il v il v pph1/2 v pplk rp# (p) ry/by# (r) data (d/q) we# (w) oe# (g) ce# (e) addresses (a) t avav t avwh t elwl t whgl t whqv1/2/3/4 t whwl t whdx d in d in a in a in high z t phwl t whrl valid srd d in t vpwh t wheh v il v hh t qvph t phhwh (note 1) (note 2) (note 3) (note 4) (note 5) (note 6) t dvwh t wlwh t whax t qvvl notes : 1. v cc power-up and standby. 2. write block erase or byte write setup. 3. write block erase confirm or valid address and data. 4. automated erase or program delay. 5. read status register data. 6. write read array command. fig. 13 ac waveform for we#-controlled write operations
lh28f008sc-v/SCH-V - 33 - notes : 1. in systems where ce# defines the write pulse width (within a longer we# timing waveform), all setup, hold, and inactive we# times should be measured relative to the ce# waveform. 2. sampled, not 100% tested. 3. refer to table 3 for valid a in and d in for block erase, byte write, or lock-bit configuration. 4. v pp should be held at v pph1/2 (and if necessary rp# should be held at v hh ) until determination of block erase, byte write, or lock-bit configuration success (sr.1/3/4/5 = 0). 5. see fig. 9 "transient input/output reference waveform" and fig. 11 "transient equivalent testing load circuit" (high seed configuration) for testing characteristics. 6. see fig. 10 "transient input/output reference waveform" and fig. 11 "transient equivalent testing load circuit" (standard configuration) for testing characteristics. symbol parameter note min. max. min. max. min. max. t avav write cycle time 85 90 120 ns t phel rp# high recovery to ce# 2111s going low t wlel we# setup to ce# going low 0 0 0 ns t eleh ce# pulse width 50 50 50 ns t phheh rp# v hh setup to ce# going high 2 100 100 100 ns t vpeh v pp setup to ce# going high 2 100 100 100 ns t aveh address setup to ce# going high 3404040ns t dveh data setup to ce# going high 3 40 40 40 ns t ehdx data hold from ce# high 5 5 5 ns t ehax address hold from ce# high 5 5 5 ns t ehwh we# hold from ce# high 0 0 0 ns t ehel ce# pulse width high 25 25 25 ns t ehrl ce# high to ry/by# going low 90 90 90 ns t ehgl write recovery before read 0 0 0 ns t qvvl v pp hold from valid srd, 2, 4 0 0 0 ns ry/by# high t qvph rp# v hh hold from valid srd, 2, 4 0 0 0 ns ry/by# high 6.2.6 alternative ce#-controlled writes (note 1) ?v cc = 5.00.25 v, 5.00.5 v, t a = 0 to +70?c or C 25 to +85 ? c versions v cc 0.25 v v cc 0.5 v (note 5) lh28f008sc-v85/ lh28f008SCH-V85 (note 6) lh28f008sc-v12/ lh28f008SCH-V12 (note 6) lh28f008sc-v85/ lh28f008SCH-V85 unit
lh28f008sc-v/SCH-V - 34 - v pp (v) v ih v ih v ih v ih v ih v oh v ol v ih v il v il v il v il v il v il v pph1/2 v pplk rp# (p) ry/by# (r) data (d/q) ce# (e) oe# (g) we# (w) addresses (a) t avav t aveh t wlel t ehgl t ehqv1/2/3/4 t ehel t ehdx d in d in a in a in high z t phel t ehrl valid srd d in t vpeh t ehwh v il v hh t qvph t phheh (note 1) (note 2) (note 3) (note 4) (note 5) (note 6) t dveh t eleh t ehax t qvvl notes : 1. v cc power-up and standby. 2. write block erase or byte write setup. 3. write block erase confirm or valid address and data. 4. automated erase or program delay. 5. read status register data. 6. write read array command. fig. 14 ac waveform for ce#-controlled write operations
lh28f008sc-v/SCH-V - 35 - v ih v oh v ol v il ry/by# (r) (a) reset during read array mode (b) reset during block erase, byte write, or lock-bit configuration (c) rp# rising timing t plph rp# (p) v ih v oh v ol v il ry/by# (r) t plrh t plph rp# (p) v ih 5 v v il v il v cc t 5vph rp# (p) fig. 15 ac waveform for reset operation reset ac specifications (note 1) notes : 1. these specifications are valid for all product versions (packages and speeds). 2. if rp# is asserted while a block erase, byte write, or lock-bit configuration operation is not executing, the reset will complete within 100 ns. 3. a reset time, t phqv , is required from the latter of ry/by# or rp# going high until outputs are valid. 4. when the device power-up, holding rp#-low minimum 100 ns is required after v cc has been in predefined range and also has been in stable there. v cc = 5.00.5 v symbol parameter note min. max. unit t plph rp# pulse low time (if rp# is tied to v cc , 100 ns this specification is not applicable) t plrh rp# low to reset during block erase, 2, 3 12 s byte write or lock-bit configuration t 5vph v cc 4.5 v to rp# high 4 100 ns 6.2.7 reset operations
lh28f008sc-v/SCH-V - 36 - v pp = 5.00.5 v v pp = 12.00.6 v symbol parameter note min. typ. (note 1) max. min. typ. (note 1) max. unit t whqv1 byte write time 2 6.5 8 tbd 4.8 6 tbd s t ehqv1 block write time 2 0.4 0.5 tbd 0.3 0.4 tbd s t whqv2 block erase time 2 0.9 1.1 tbd 0.3 1.0 tbd s t ehqv2 t whqv3 set lock-bit time 2 9.5 12 tbd 7.8 10 tbd s t ehqv3 t whqv4 clear block lock-bits time 2 0.9 1.1 tbd 0.3 1.0 tbd s t ehqv4 t whrh1 byte write suspend latency time to read 5.6 7 5.2 7.5 s t ehrh1 t whrh2 erase suspend latency time to read 9.4 13.1 9.8 12.6 s t ehrh2 notes : 1. typical values measured at t a = +25?c and nominal voltages. assumes corresponding lock-bits are not set. subject to change based on device characterization. 2. excludes system-level overhead. 3. these performance numbers are valid for all speed versions. 4. sampled, not 100% tested. 6.2.8 block erase, byte write and lock-bit configuration performance (note 3, 4) ?v cc = 5.00.25 v, 5.00.5 v, t a = 0 to +70?c or C 25 to +85 ? c
lh28f008sc-v/SCH-V - 37 - lh28f008sc (h) t-v85 device density 008 = 8 m-bit access speed (ns) 85 : 85 ns (5.0 0.25 v), 90 ns (5.0 0.5 v), 12 : 120 ns (5.0 0.5 v) limited voltage option v = 5 v v cc only package t = 40-pin tsop (i) (tsop040-p-1020) normal bend r = 40-pin tsop (i) (tsop040-p-1020) reverse bend n = 44-pin sop (sop044-p-0600) b = 48-ball csp (fbga048-p-0608) architecture s = symmetrical block power supply type c = smart 5 technology operating temperature blank = 0 to +70 c h = ?5 to +85 c product line designator for all sharp flash products valid operational combinations v cc = 5.00.5 v v cc = 5.00.25 v option order code 100 pf load, 30 pf load, ttl i/o levels 1.5 v i/o levels 1 lh28f008scxx-v85 90 ns 85 ns 2 lh28f008scxx-v12 120 ns 7 ordering information
packaging 0.2 0.05 0.1 max. 0.2 typ. 1 package base plane 20.0 0.3 19.0 0.3 0.125 0.125 0.435 40 21 20 10.0 18.4 p _ 0.5 1.20 0.115 40 _ 0.2 0.08 0.10 0.08 m 0.995 0.1 40 tsop (tsop040-p-1020)
packaging 13.2 16.0 1.27 44 _ 0.4 44 1 23 22 0.15 (14.4) 0.1 typ. 0.4 0.2 0.05 0.15 m 0.15 28.2 2.7 1.275 0.2 0.1 0.2 0.15 0.1 package base plane 44 sop (sop044-p-0600)
packaging a b 6.0 0 + 0.2 s 8.0 + 0.2 0 1.2 max. 0.35 0.05 0.1 s d 0.45 0.03 c 0.8 typ. 0.4 typ. 1.0 typ. 0.8 typ. 0.4 typ. 0.1 s * 0.4 typ. 1.2 typ. 8 f a 1 s m 0.30 * land hole diameter for ball mounting ab scd m 0.15 / / 48 csp (fbga048-p-0608)

▲Up To Search▲

Price & Availability of SCH-V

	To Download SCH-V Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .